model.rtw (Target Language Compiler)

Target Language Compiler

State Mapping Information

All continuous and discrete states contained within your model are conceptually grouped into a single vector, referred to as X (and rtX in the generated code). Blocks can directly connect to the state vector by using state ports. The StatesMap provides a mapping for these types of connections. The format of the StatesMap may change in a future release.

Table A-13: Model.rtw State Mapping Information
Variable/Record Name
Description

StatesMap

Matrix of dimension (N,3), where N = total number of state ports in your model. Block signal sources that come from a state vector (e.g., SignalSrc X4) use the StatesMap to locate their source block. For example, "SignalSrc X4" means the fifth row of the StatesMap, not the fifth index into the conceptual model state vector.

**Table A-13: Model.rtw State Mapping Information**
Variable/Record Name	Description
`StatesMap`	Matrix of dimension `(N,3)`, where `N` = total number of state ports in your model. Block signal sources that come from a state vector (e.g., `SignalSrc X4`) use the `StatesMap` to locate their source block. For example, "`SignalSrc X4`" means the fifth row of the `StatesMap`, not the fifth index into the conceptual model state vector.

Data Type Work (DWork) Information Block Record Defaults